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ASAHI KASEI
[AKD4114-B]
AKD4114-B
AK4114 Evaluation Board Rev.0
GENERAL DESCRIPTION AKD4114-B is the evaluation board for AK4114, 192kHz digital audio transceiver. This board has optical and BNC connector to interface with other digital audio equipment. Ordering guide
AKD4114-B --Evaluation board for AK4114 (A cable for connecting with printer port of IBM-AT compatible PC and a control software are packed with this. The control software does not operate on Windows NT.)
FUNCTION Digital interface -S/PDIF : 8 channel input (optical or BNC) 2 channel output (optical or BNC ) - Serial audio data I/F : 1 input/output (for DIR deta output/DIT data input. 10-pin port) -B,C,U,V bit : 1 input/output port (10-pin port) -Serial control data I/F 1 input/output port (10-pin port)
5V Opt RX0 REG 3.3V GND Control
RX1 RX7 TX0 TX1 Opt
AK4114
B,C,U,V
Serial Data out (For DIR)
Figure 1. AKD4114-B Block Diagram *Circuit diagram and PCB layout are attached at the end of this manual.
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2005/12
ASAHI KASEI
[AKD4114-B]
Evaluation Board Manual
Operating sequence (1) Set up the power supply lines. [+ 5V] (Red) = 5V [GND] (Black) = 0V Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode and jumper pins. (Refer to the following item.) (3) Connect cables. (Refer to the following item.) (4) Power on. The AK4114 should be reset once bringing PDN(SW2) "L" upon power-up.
Evaluation modes (1) Evaluation for DIR (Default) S/PDIF in (optical or BNC) - AK4114 - Serial Data out (10pin port)
MCLK BICK LRCK SDTO
S/PDIF
Optical, XLR or BNC connector
AK4114 (DIR)
PORT2 (10pin Header)
MCLK BICK LRCK SDTO
DAC
AKD4114-B
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector(PORT1: TORX176) or BNC connector. The AKD4114-B can be connected with the AKM's DAC evaluation board via 10-line cable. a. Set-up of Bi-phase Input RX0 and RX1-7 should not select BNC at the same time. a-1. RX0 Connector Optical (PORT1) BNC (J2)
JP2(RXP0) JP3(RXN0) OPT BNC BNC BNC Table 1. Set-up of RX0
a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only. Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be Short. Input JP RX1 JP4 Short RX3 RX4 RX5 RX2 JP6 JP7 JP8 JP5 Short RX4 RX5 Short Table 2. Set-up of RX1, 2, 3, 4, 5, 6 and 7 RX6 JP9 RX6 RX7 JP10 RX7
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ASAHI KASEI
[AKD4114-B]
a-3. Set-up of AK4114 input path It sets up by SW 1_1 and SW 1_5 in parallel mode. Please set up IPS2-0 bits in serial mode. IPS1 pin IPS0 pin (SW1_5) (SW1_1) INPUT Data IPS2 bit IPS1 bit IPS0 bit 0 0 0 RX0 0 0 1 RX1 0 1 0 RX2 0 1 1 RX3 1 0 0 RX4 1 0 1 RX5 1 1 0 RX6 1 1 1 RX7 (In parallel mode, IPS2 is fixed to "0") Table 3. Recovery Data Select -
Default
b.
Set-up of clock input and output The signal level outputted/inputted from PORT2 is 3.3V.
MCLK SDTO LRCK BICK PORT2 DIR 1
5
GND
GND
GND
Figure 2. PORT2 pin layout b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 is selected by OCKS 1-0. Output JP12 signal Default MCKO1 MCKO1 MCKO2 MCKO2 Table 4. Set-up of MCKO1/MCKO2
OCKS1 pin (SW3_2) OCKS1 bit 0 0 1 1
OCKS0 pin (SW3_3) OCKS0 bit 0 1 0 1
(X'tal)
MCKO1
NC
10
GND
6
MCKO2
fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default
256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table 5. Master Clock Frequency Select
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2005/12
ASAHI KASEI
[AKD4114-B]
b-2. Set-up of input/output of BICK and LRCK Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4114 (Refer to Table 7). Audio format SW3_7 (DIR_I/O) Slave mode 0 Master mode 1 Table 6. Set-up of DIR_I/O c. Set-up of Audio format It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode. DIF2 pin (SW1_4) DIF2 bit 0 0 0 0 1 1 1 1 DIF1 pin (SW1_3) DIF1 bit 0 0 1 1 0 0 1 1 DIF0 pin (SW1_2) DIF0 bit 0 1 0 1 0 1 0 1 LRCK I/O 24bit, Left 16bit, Right justified justified 24bit, Left 18bit, Right justified justified 24bit, Left 20bit, Right justified justified 24bit, Left 24bit, Right justified justified 24bit, Left 24bit, Left justified justified 24bit, I2S 24bit, I2S 24bit, Left 24bit, Left justified justified 24bit, I2S 24bit, I2S Table 7. Audio format H/L H/L H/L H/L H/L L/H H/L L/H O O O O O O I I 64fs 64fs 64fs 64fs 64fs 64fs 64-128fs 64-128fs BICK I/O O O O O O O I I Default
Default
Mode 0 1 2 3 4 5 6 7
DAUX
SDTO
d.
Set-up of CM1 and CM0 The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and JP18. In serial mode, it can be selected by CM1-0 bits. CM1 pin (SW3_1) CM1 bit 0 0 1 1 CM0 pin (JP18) CM0 bit 0 (CM0) 1 (CDTO/CM0=H) 0 (CM0) 0 1 ON OFF ON ON ON(Note) ON ON ON Clock source PLL(RX) X'tal PLL(RX) X'tal SDTO source RX DAUX RX DAUX Default
(UNLOCK)
PLL
X'tal
1 (CDTO/CM0=H) ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X'tal is not used as clock comparison for fs detection (XTL0, 1= "1,1"), the X'tal is OFF. Table 8. Clock Operation Mode Select
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ASAHI KASEI
[AKD4114-B]
(2) Evaluation for DIT Serial Data in(10pin port) - AK4114 - S/PDIF out(optical or BNC)
MCLK BICK LRCK DAUX
ADC
PORT2 (10pin Header)
MCLK BICK LRCK DAUX
AK4114 (DIT)
Optical, XLR or BNC connector
S/PDIF
AKD4114-B
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT2: DIR). The AKD4114-B can be connected with the AKM's DAC evaluation board via 10-line cable. a. Set-up of a Bi-phase output signal TX0 and TX1 should not select an optical connector or a BNC connector at the same time. a-1. The data outputted from TX1 can be selected by OPS12-10 bit. Connector JP19 (TX1) Optical (PORT4) OPT BNC (J4) BNC Table 9. Set-up of TX1 JP14 (TX1) BNC BNC
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In serial mode, it can be selected by OPS02-00 bits. Connector Optical (PORT4) BNC (J4) JP13 (TX0) JP19 (TXP1) OPT Open BNC Open Table 10. Set-up of TX0 JP14 (TXN1) BNC BNC
b.
Set-up of clock input and output The used signals are MCKO1, MCKO2, LRCK, BICK, ELRCK and DAUX. The signal level outputted and inputted from PORT2 and PORT5 is 3.3V. Clock PORT MCLK PORT2 BICK PORT2 LRCK PORT2 DAUX PORT2 Table 11. Clock input/output b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 sets up by OCKS 1-0. Output JP12 JP15 JP11 signal MCKO1 MCKO1 MCKO MCKO1 MCKO2 MCKO2 MCKO MCKO2 Table 12. Selection of MCKO1/MCKO2
Default
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2005/12
ASAHI KASEI
[AKD4114-B]
OCKS1 pin (SW3_2) OCKS1 bit 0 0 1 1
OCKS0 pin (SW3_3) OCKS0 bit 0 1 0 1
(X'tal)
MCKO1
MCKO2
fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default
256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table 13. Master Clock Frequency Select
b-2. Set-up of input/output of BICK and LRCK Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4114 (Refer to Table 20). JP16 and 17 should be fixed to the "DC" side. Audio format SW3_8 (DIT_I/O) Slave mode 0 Master mode 1 Table 14. Set-up of DIT_I/O
Default
c.
Set-up of audio data format Please refer to Table 7.
d.
Set-up of CM1 and CM0 CM1 pin (SW3_1) CM1 bit 0 0 1 1 CM0 pin (JP18) CM0 bit 0 1 0 1 SDTO source RX DAUX RX DAUX Default
(UNLOCK) 0 1
PLL ON OFF ON ON
X'tal ON(Note) ON ON ON
Clock source PLL(RX) X'tal PLL(RX) X'tal
ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X'tal is not used as clock comparison for fs detection (XTL0, 1= "1,1"), the X'tal is OFF. Table 15. Clock Operation Mode Select
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ASAHI KASEI
[AKD4114-B]
B, C, U, V Inputs and output
B(block start), C(channel status), U(user data) and V(validity) are inputted/outputted via 10pin header (PORT3: BCUV). Pin arrangement of PORT3 has become like Figure 3.
VOUT VIN GND GND PORT3 BCUV 10
C
U
B
6
GND
GND
GND
1
Figure 3. PORT3 pin layout
Serial control
The AK4114 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6 (uP-I/F) with PC by 10-line flat cable packed with the AKD4114-B. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT6 is as Figure 4.
Mode SW1_6 JP18 CDTO/CM0="H" 4 wire Serial L SDA and CM0="L"(Note) IIC H Note: In IIC mode, the chip address is fixed to "01". Table 16. Set-up of Parallel mode and Serial mode
GND GND GND GND PORT6 uP I/F 2
GND
5
10
1
Figure 4. PORT6 pin layout This evaluation board encloses control software. A software operation procedure is included in an evaluation board manual.
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CDTO
CCLK CSN
NC
CDTI
9
2005/12
ASAHI KASEI
[AKD4114-B]
Toggle switch set-up SW2 PDN Reset switch for AK4114. Set to "H" during normal operation. Bring to "L" once after the power is supplied.
LED indication LE1 INT0 LE2 INT1
Bright when INT0 pin goes to "H". Bright when INT1 pin goes to "H".
DIP switch (SW1) set-up: -off- means "L" No. Switch Name Function 1 IPS0 Set-up of IPS0 pin. (in parallel mode) 2 DIF0 Set-up of DIF0 pin. (in parallel mode) 3 DIF1 Set-up of DIF1 pin. (in parallel mode) 4 DIF2 Set-up of DIF2 pin. (in parallel mode) Set-up of IPS1 pin. (in parallel mode) 5 IPS1/IIC Set-up of IIC pin. (in serial mode) "L": 4 wire Serial, "H": IIC Set-up of P/SN pin. "L": Serial mode, "H": Parallel mode 6 P/SN 7 TEST Don't care 8 ACKS Don't care DIP switch (SW3) set-up: -off- means "L" No. Switch Name Function 1 CM1 Set-up of CM1 pin. (in parallel mode) 2 OCKS1 Set-up of OCKS1 pin. (in parallel mode) 3 OCKS0 Set-up of OCKS0 pin. (in parallel mode) 4 PSEL Don't care 5 XTL0 See Table 17 6 XTL1 Set-up of the transmission direction of 74AC245 DIR_I/O "L": When inputting from PORT2, "H": When outputting from 7 PORT2 8 DIT_I/O Don't care
Default OFF OFF ON ON OFF OFF OFF OFF
Default OFF OFF OFF OFF OFF OFF ON OFF
Set-up of XTL1 and XTL0 SW3_6 SW3_5 X'tal Frequency XTL1 XTL0 X'tal 0 0 11.2896MHz 0 1 12.288MHz 1 0 24.576MHz 1 1 (Use channel status) Table 17. Set-up of XTL1 and XTL0
Default
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2005/12
ASAHI KASEI
[AKD4114-B]
Jumper set up. No. Jumper Name 1 D3V/VD
2 4,5,6 7,8,9,10
RXP0 RX1-3 RX4-7 DIR MCLK , DIT MCLK TX0
11,12
13
15
MCLK
18
SDA/CDTO
19
TXP1
Function Set-up of Power supply source for 74AC245. D3V : D3V (default) VD : VD Set-up of RXP0 input circuit. OPT : Optical (default) BNC : BNC Set-up of RX1-3 input circuit. RX4-7 set-up depending serial/parallel mode RX4-7 : Serial mode (default) DIF2-0,IPS0 : Parallel mode MCKO set-up for PORT5(DIT) and PORT2(DIR) MCKO1 : MCKO1 of AK4114 (default) MCKO2 : MCKO2 of AK4114 Set-up of TX0 output circuit. OPT : Optical BNC : BNC (default) MCLK input output selection of PORT5(DIT). MCKO : MCKO (default) EMCK : EMCK Set-up of SDA/CDTO pin. 4 wire Serial : CDTO/CM0="H". (default) IIC : SDA Set-up of TXP1 input circuit. OPT : Optical (default) BNC : BNC
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2005/12
ASAHI KASEI
[AKD4114-B]
Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4114-B according to previous term. 2. Connect IBM-AT compatible PC with AKD4114-B by 10-line type flat cable (packed with AKD4114-B). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AKD4114-B Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4114-B0.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Write default" button. 3. Then set up the dialog and input data.
Explanation of each buttons
1. [Port Setup] : 2. [Write default] : 3. [All Write] : 4. [Read All] : 5. [Function1] : 6. [F3] : 7. [SAVE] : 8. [OPEN] : 9. [Write] : 10. [Read] : Set up the printer port. Initialize the register of AK4114. Write all registers that is currently displayed. All the registers of AK4114 are read. Dialog to write data by keyboard operation. Dialog of sequential writing. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. The data corresponding to each register is read.
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ASAHI KASEI
[AKD4114-B]
Explanation of each dialog
1. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4114, click "OK" button. If not, click "Cancel" button. 2. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4114, click "OK" button. If not, click "Cancel" button.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
Attention on the operation
If you set up Function1 dialog, input data to all boxes. Attention dialog is indicated if you input data or address that is not specified in the datasheet or you click "OK" button before you input data. In that case set up the dialog and input data once more again. These operations does not need if you click "Cancel" button or check the check box.
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2005/12
ASAHI KASEI
[AKD4114-B]
Revision History
Date (YY/MM/DD) 04/11/22 05/06/21 05/12/22 Manual Revision KM076600 KN076601 KM076602 Board Revision 0 0 0 Reason First edition Modification Modification Circuit diagram was changed Block diagram at DIR/DIT Evaluation was added. Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
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5
4
3
2
1
C N4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
RX3
RX2
RX1
RX0
P/SN
D
IPS0/RX4
AVDD
49
D
P/SN C19 2 C20 0.1u C N1 +
1 10u
2
1
DIF0/RX5
1
C21 0.47u
R61 18k
C N3
47
43
45
41
48
46
44
42
39
38
40
37
U7
TEST1
VCOM
2
AVDD
AVSS
AVSS
AVSS
INT1
RX3
RX2
RX1
RX0
R
3
DIF1/RX6
1
IPS0/RX4
4
PDN
P DN
2
AVSS
C
5
DIF2/RX7
3
DIF0/RX5
6
4
TEST2
7
VIN
5
DIF1/RX6
8
DAUX
DAUX
6
AVSS
9
X1
2
7
AK4114
DIF2/RX7
10
IPS1/IIC
XTO
1
MCKO1
MCKO1
IP S1/IIC
8
11
MCKO2
MCKO2
P/SN
9
P/SN
12
B
XTL0
10
XTL0
13
XTL1
11
XTL1
14
BICK
B ICK
12
VIN MCKO1 DVDD COUT UOUT BOUT VOUT TVDD DVSS LRCK TX0 TX1
15
SDTO
NC
SDTO
13
14
15
16
17
18
19
20
21
22
23
16
LRCK
LRCK
24
C24 0.1u C26 2 10u + +
1
1
TX0
BOUT
COUT
UOUT
VOUT
TX1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
OVDD
A
31
32
C N2
5
4
3
+
48
XTL1
XTL1
47
INT0
36
XTL0
XTL0
46
OCKS0/CSN/CAD0
35
45
OCKS1/CCLK/SCL
34
IP S1/IIC
IPS1/IIC
44
C
CM1/CDTI/SDA
33
43
CM0/CDTO/CAD1
32
42
PDN
31
P DN
41
XTI
30
C22 5p C23 5p
OCKS0/CSN/CAD
40
29
OCKS1/CCLK/SCL
39
11.2896MHz
DAUX 28
DAUX
CM1/CDTI/SDA
38
MCKO2
27
MCKO2
CM0/CDTO/CAD1
37
B
BICK
26
B ICK
INT1
36
SDTO
25
SDTO
INT0
35
34
C25 0.1u C27 2 10u
33
LRCK MCKO1
A
Title Size A3 D ate:
2
AKD4114
Document Number R ev
SUB
Monday, November 22, 2004 Sheet
1
A
3 of 3
5
4
3
2
1
CN1 JP1 PORT1 D3V VD C5 C6
For U6
VD D3V
For U1, U2, U5
D3V VD
For U3, U4
D3V/VD
6 5
6 5
GND VCC GND OUT
4 3 2 1
L1
10u
VD
49 50 R1 JP2 51 OPT XLR BNC 1 3 5 2 4 6 AVDD P/SN/ANS ACKS AVDD 52
D
C7
C8 +
TORX176 C1 C2 C3 C4
0.1u
10u
0.1u
D
0.1u0.1u0.1u
0.1u 0.1u
470
P/SN/ANS
53 54 55 56 57
T2 LP2950A R3 GND AVDD 1 OUT IN 3
ACKS
+5V L2
10u
TVDD/VDD
RXN0
short
+
RXP0 R4 VD
C11 47u
2
short
T3 TA48M33F R6 DVDD OUT GND IN + C15 47u
J2
RX0
R5
C13 RX1 58 59 60 61
75
+
0.1u
JP4 AVDD JP5 RX2 JP6 AVDD
short
R7 OVDD
C14 47u
short
C
R8 D3V
short
IPS0 DIF0 DIF1 DIF2/XSEL IPS1/IIC P/SN/ANS TEST ACKS RP1 1 2 3 4 5 6 7 8 9 47k
SW1
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D3V
JP7 RX4 IPS0 RX3 62 63 64
C
AVDD
AVDD
IPS0/RX4 JP8 RX5 DIF0 IPS1/IIC P/SN/ANS TEST ACKS DIF0/RX5 JP9 RX6 DIF1 JP10 RX7 DIF2/XSEL R9 TEST TEST
CN2 1 2 3 4 5 6
B
DIF1/RX6
PDN
DIF2/XSEL/RX7
B
D3V U1 2 3 5 6 11 10 14 13 15 1 1A 1B 2A 2B 3A 3B 4A 4B G A/B 74LVC157 1Y 2Y 3Y 4Y 4 7 9 12 H L
10k D1 1S1588
1 74HC14 U2A 2 3 74HC14 JP11 MCKO1 MCKO MCKO2 U2B
DVDD VIN
DVDD
VIN
7 8 9
R10
4 DAUX2
DAUX
100
EMCK1
100 100
R11 R12
EMCK2 DAUX2
C16 SW2
PDN
0.1u
MCKO1
10 11 12 13
MCKO2
DIT_MCLK DIR_MCLK
JP12 MCKO1 MCKO2
100 100 100 100 100
R13 R14 R17 R19 R21
DVDD
OVDD
GND GND GND GND GND
PORT2 10 9 8 7 6
1 2 3 4 5
MCLK BICK LRCK SDTO DAUX R22 R23
100 100 100 100
R15 R16 R18 R20
U3 18 17 16 15 14 13 12 11 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A2 A3 A4 A5 A6 A7 DIR OE 74AC245 2 3 4 5 6 7 8 9 1 19 DIR_I/O
BICK
14 15 16
A
SDTO
DIR
A
LRCK
100k
100k
100k
Title Size A3 Date:
5 4 3 2
AKD4114-B
Document Number Rev
MAIN
Friday, November 19, 2004 Sheet
1
0
1 of 2
5
4
3
2
1
PORT3 JP19 OPT XLR BNC 1 3 5 TXP1 2 4 6 1 2 3 4 5 10 9 8 7 6
CN3
B C U VOUT VIN
R24 R25 R26 R27 R28
100 100 100 100 100
B
17 18 19 20
D
C VIN U
BCUV
R29 R30 R31 R32 JP13
D
47k 47k 47k 47k
TVDD/VDD
VOUT
TVDD
PORT4
5 6 5 6 IN VCC IF GND 4 3 2 1 VD
TX0
21 22 23 24 25
OPT TX0
TOTX176
R33 1k
C17
TXP1
0.1u
TXN1
J4
T5
TX0
DA02-F
R36
R37 1:1
240
26 27 28 29 OVDD OVDD 30 31 EBICK 32
150
C
C
CN4 U2C LE1 R45 6 5 74HC14 INT0 U2D LE2 D3V R47 8 9 74HC14 VD R51
B
EMCK2
EMCK
33 34 35 36 37 38
B
ELRCK
INT0
1k
INT1 U5
INT1
1k
R48
CM0/CDTO/CAD1 1Y 2Y 3Y 4Y 4 7 9 12 1 74LS07 74LVC157 D3V JP18 R57 DVDD DVDD R50 R53 U6A 2
10k 10k 10k
R49 R52 R55
470 470 470
R54 PORT6 10 8 6 4 2 9 7 5 3 1
CSN R56 SCL/CCLK 51 SDA/CDTI SDA(ACK)/CDTO
2 3 5 6 11 10 14 13 15 1
1A 1B 2A 2B 3A 3B 4A 4B G A/B
100 100
CM1/CDTI/SDA
OCKS1/CCLK/SCL
39 40 41 42
OCKS0/CSN/CAD0
P/SN/ANS
uP-I/F
D3V
R58
10k
R60
R59
10k
CM1/FS1 OCKS1/FS2 OCKS0/FS0 PSEL XTL0/CKS1 XTL1/TRANS DIR_I/O DIT_I/O RP2 1 2 3 4 5 6 7 8 9 47k
SW3
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D3V
SDA CDTO/CM0=H CM0=L
100
43
SDA/CDTO
100
IPS1/IIC
IPS1/IIC
44 45 46 47 48
A
PSEL D3V/VD
XTL0
XTL1
A
DIR_I/O DIT_I/O Title Size A3 Date:
5 4 3 2
AKD4114-B
Document Number Rev
MAIN
Tuesday, June 21, 2005 Sheet
1
0
2 of 2
AKD4115-A L1
AKD4115-A L1_SILK

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Price & Availability of AKD4114-B

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